International Conference on VLSI Design , January 1997 Dynamic Fault Grouping for PROOFS : A Win for Large Sequential

This paper discusses the important role of fault grouping in a parallel 32-bit fault simulator such as PROOFS. Three algorithms are presented which dynamically order the fault list during fault simulation to determine how the faults get grouped together. The dynamic fault grouping algorithms were incorporated into PROOFS and tested on benchmark circuits. The algorithms showed a marked reduction in the number of faulty circuit gate evaluations (compared to a static fault grouping) for almost all of the circuits with more than 20 ip-ops. For the largest benchmark circuit, s35932, all of the algorithms showed at least a 39% reduction in the number of faulty circuit gate evaluations and at least a 55% speedup in simulation time. This section will explain the importance of fault grouping in determining the fault simulation eeciency of a parallel 32-bit fault simulator. Then, some limitations of static fault grouping will be presented. In order to take advantage of the parallelism inherent in PROOFS, the proper fault grouping is essential 1] 2]. Each fault injected into the circuit causes a certain number of circuit elements to be evaluated. Let the list of all circuit elements evaluated for a given fault and vector pair be called the sphere of innuence. The goal of fault grouping is to group faults together whose spheres of innuence have the greatest intersection. When a group of 32 faults is injected into a circuit , all the gates in each of the 32 spheres of innuence must be evaluated before a new group of faults can be injected into the circuit. In the case of ideal fault grouping (where all 32 faults grouped together cause exactly the same circuit elements to be simulated) the number of gate evaluations is reduced by a factor of 32 because each gate must be evaluated only once to simulate every fault in the fault group. On the other hand, if there is no intersection between spheres of in-uence, then each gate is evaluated to determine the value of one faulty circuit only. When this occurs, the major advantage of parallel fault simulation is lost. In a fault simulator that uses word level parallelism, such as PROOFS, the fault grouping that is chosen will determine the number of gate evaluations that must be performed and thus aaect the fault simulation time. PROOFS implements a static fault grouping technique based on a depth-rst search of the circuit …